/******************************************************************************
*
* MODULE:    fOnda.v
* DEVICE:     
* PROJECT:   Tarea 1 Diseño Electronico Digital
* AUTHOR:    Ricardo Dávila Castro   
* DATE:      2010 19:35:08
*
* ABSTRACT:  Formas de ONDA Ejercicio Uno
*            
*******************************************************************************/

`ifndef 	F_ONDA
`define    F_ONDA

module fOnda;
  
reg clk_100M;
reg arst_n;
reg in1;
reg in2;
reg  Direccion =  0 ;
reg [3:0] SignalConteo = 0;
reg [7:0] SignalAchtBit;


parameter PERIOD = 5;

initial
	 begin 
		arst_n = 1'b1;
		repeat (2)  #20 arst_n = ~arst_n;
	 end
 
initial 
	begin 
		in1 = 1'b1;
		#5 in1 = ~in1;
		forever 
			begin 
				#20 in1 = ~in1;
				#10 in1 = ~in1;
			end
	end

initial 
	begin 
		in2 = 1'b0;
		#45 in2 = ~in2;
		#10 in2 = ~in2;
		#10 in2 = ~in2;
		#20 in2 = ~in2;
		//#20 in2 = ~in2;
	end
        
initial 
	begin
		clk_100M = 1'b0;
		forever #PERIOD clk_100M = ~clk_100M;
	end		

always @ (posedge clk_100M)
	begin
		if (Direccion)
			SignalConteo <= SignalConteo - 1;
		else
			SignalConteo <= SignalConteo + 1;
			if (SignalConteo==8)
			  Direccion <= 1;
			 else if (SignalConteo==1)
			  Direccion <= 0; 			
	end

/*
initial
	begin
	Direccion =0;
	#170 Direccion = ~Direccion;
	end

always @ (posedge clk_100M)
	begin
		if (Direccion)
			if (SignalConteo<=9 && SignalConteo>0)
			SignalConteo <= SignalConteo - 1;
			else ; // ya termino la cuenta
		else 	
			if (SignalConteo>=0 && SignalConteo<9)
			SignalConteo <= SignalConteo + 1;
			else ; // ya termino la cuenta
			
	end
*/	
always @ (posedge clk_100M)
  	begin
  		SignalAchtBit <= {$random} % 15;  
  	end
  
endmodule
`endif